Questa One Sim Xact enables much quicker gate-level simulation bring-up by automatically eliminating pesky false Xs, zero-delay race conditions and library modeling errors, while isolating hard to diagnose connectivity problems. Plus, it supports advanced real X root cause tracing tools.
Formal-enhanced logic simulation dynamically performs X-pessimism analysis, analyzes X propagation in datapaths and gated clock logic and repairs on the fly.
Zero-delay GLS may demonstrate race conditions, especially in designs with gated clocking and delay lines. The "pseudo-SDF" generator efficiently solves race condition issues without the need to modify cell libraries.
Force/release propagation analysis confirms when forces have been optimized away and no longer drive any fanout logic. Connectivity analysis finds modules with undriven inputs that are creating X sources.
Questa One Sim Xact delivers an enhanced methodology for bringing up gate-level simulation quickly and easily. Its patented technology can effectively analyze a simulation using combinatorial analysis to determine if X values at D-inputs of a flip-flop are false due to X-pessimism or real. It automatically eliminates the false X's which allow the gate-level simulation to produce the correct results.
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