Oasys-RTL provides better quality of results by enabling physical accuracy, floorplanning, and fast optimization iterations to get to design closure on time.
The power-aware synthesis capabilities include support for multi-threshold libraries, automatic clock gating, and UPF based Multi-VDD flow. During synthesis Oasys-RTL inserts all the appropriate level shifters, isolation cells and retention registers depending on the power intent as defined in the UPF.
Oasys-RTL can create a floorplan directly from the design RTL using design dataflow and timing, power, area, and congestion constraints. It considers regions, fences, blockages and other physical guidance using the advanced floorplan editing tools and automatically places macros, pins, and pads.
Rather than synthesizing first, then trying to optimize the gates, Oasys-RTL concurrently optimizes higher-level RTL partitions where it has a greater ability to converge on the best solution.
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