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Overview

ModelSim

ModelSim simulates behavioral, RTL, and gate-level code - delivering increased design quality and debug productivity with platform-independent compile. Single Kernel Simulator technology enables transparent mixing of VHDL and Verilog in one design.

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ModelSim simulates behavioral, RTL, and gate-level code - delivering increased design quality and debug productivity with platform-independent compile. Single Kernel Simulator technology enables transparent mixing of VHDL and Verilog in one design.
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Key features

Native compiled, single kernel simulator technology

ModelSim packs an unprecedented level of verification capabilities into a cost-effective HDL simulator and is ideally suited for the verification of small and medium-sized FPGA designs – especially designs with complex, mission-critical functionality.

Advanced code coverage

Fast time to coverage closure

ModelSim’s advanced code coverage capabilities provide valuable metrics for systematic verification. Plus, ModelSim’s ease of use lowers the barriers for leveraging verification resources. All coverage information is stored in the highly efficient UCDB database. Coverage results can be viewed interactively, post-simulation, or after a merge of multiple simulation runs.

Mixed HDL simulation

Mixed language simulation

Comprehensive support of Verilog, SystemVerilog for Design, VHDL, and SystemC provide a solid foundation for single and multi-language design verification environments. An easy-to-use and unified environment provides FPGA designers the advanced capabilities they need for debugging and simulation.

Intuitive debug environment

Fast time-to-debug

ModelSim eases the process of finding design defects with an intelligently engineered debug environment that efficiently displays design data for analysis and debug of all hardware description languages. A broad set of intuitive capabilities for Verilog, VHDL and SystemC make it the ideal choice for ASIC and FPGA design.

ModelSim resources

Featured white papers

UVM & SystemVerilog

Upcoming and on-demand events

View all available UVM & SystemVerilog video recordings at the Verification Academy.

Whether you're an RTL design or verification engineer, this session will provide you with the knowledge and skills you need to take your work to the next level.
SVA implementation & code examples
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Introduction to SystemVerilog Assertions

ON-DEMAND WEBINAR

In this webinar, you will learn how to implement concurrent assertions using SystemVerilog Assertions (SVA), and gain a deeper understanding of how they can complement your existing verification methodologies.

Ensuring functional correctness is still one of the biggest challenges for both the ASIC/IC and FPGA markets. To quantify this, every two years, Siemens EDA commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world.
Latest industry ASIC & FPGA trends
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Wilson Research - 2022 Functional Verification Study

ON-DEMAND WEBINAR

Harry Foster highlights the key findings from the 2022 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends in ASIC and FPGA design and verification.

Create a UVM Testbench in a Day Using a Rapid, Repeatable Approach
Rapid testbench creation
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Create a UVM testbench in a day - repeatable approach

ON-DEMAND WEBINAR

In this webinar, you will learn how the UVM Framework and Questa Verification IP enables
testbench creation in a day so the team can focus on creating tests and closing coverage.

A man uses a tablet to control two robotic arms on the floor of a manufacturing facility
Write proxy-driven testbenches
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Easy Test Writing with a Proxy-driven Testbench

ON-DEMAND WEBINAR

In this webinar, we'll examine ways to create powerful reusable testbenches by hiding the signals and providing your test writers with a proxy that lets them start writing tests immediately.

UVM coding guidelines: tips & tricks you probably didn’t nnow
Do’s and don’ts of UVM sequences
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UVM coding guidelines - tips and tricks

ON-DEMAND WEBINAR

In this webinar, you will learn how to create testbench transactions and component classes that are easily debugged and reused. Additional rules are shown for SystemVerilog code to prevent common bugs.

Taking SystemVerilog arrays to the next dimension
Learn vectors & arrays differences
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Taking SystemVerilog arrays to the next dimension

ON-DEMAND WEBINAR

In this webinar, you will learn that SystemVerilog has many dynamic data & array types. You will be shown which ones to choose for scoreboards, sparse memories, hash arrays, testbenches and more.

Get your bits together: SystemVerilog structures and packages
Structures for modeling hardware
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SystemVerilog Structures and Packages

ON-DEMAND WEBINAR

In this webinar, learn how you can model hardware registers down to the bit level, or build complex data types that contain a mix of different elements such as 4-state logic, 2-state integers, real numbers, and enumerated types.

Stimulating simulating: UVM transactions
Extending your transaction classes
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Stimulating simulating: UVM transactions

ON-DEMAND WEBINAR

In this webinar, you will learn how to create classes for UVM transactions, also known as sequence items. You will also be shown where are these created and used in a testbench, and what class should you start with.

Stimulating simulating 2: UVM sequences
Stimulus with virtual sequences
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Stimulating simulating 2: UVM sequences

ON-DEMAND WEBINAR

In this webinar, you will learn to create classes for UVM sequences, containing one or more transactions, how a test class starts a sequence and how transactions flow to and from the sequence into the rest of the testbench.

Verilog basics for SystemVerilog constrained random verification.
Learn to parse Verilog expressions
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Verilog basics for SystemVerilog constrained random

In this webinar you will learn the two of the most common issues when constraint solver results do not match your intent: how Verilog expression evaluation rules apply and the affect probability has on choosing solution values.

UVM 1800.2 & the new and improved UVM cookbook.
Key additions in UVM 1800.2
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UVM 1800.2 & the new and improved UVM cookbook

ON-DEMAND WEBINAR

In this webinar, you will learn the changes in UVM 1800.2 from UVM 1.2 and 1.1d so you can be prepared to embrace the new Standard. We'll cover key additions in UVM 1800.2 and what’s in the new UVM Cookbook.

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Get in touch with our sales team 1-800-547-3000 or 1-503-685-8000

Verification Academy

Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.

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Verification Horizons blog

Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

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Verification Horizons

The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

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