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Gencellicon

Constraints Certifier

A sign-off constraints platform provides demotion, budgeting and hierarchical equivalency of timing constraints at any stage of the ASIC or FPGA flow. Constraints certifier provides comprehensive capabilities to validate constraints and timing exceptions with respect to underlying HDL.

Advanced timing constraint capabilities with Excellicon

Acquisition enables SoC designers to accelerate design closure and enhance constraint correctness with management.

Why Constraints Certifier

Constraints Certifier uses formal algorithms to verify the timing constraints, thus providing accurate in-depth analysis of both the design and its associated timing constraints. Using a formal engine to analyze the behavior of the design and the SDC files reduces noise and false warnings associated with static checking methods. Designers can generate incremental SDC in case the original SDC is missing constraints. When dealing with designer intent in the associated SDC file, SVAs can capture the requirements for further simulation for precise results.

Frequently asked questions

Timing equivalence checking is traditionally referred to as top-to-block checking of timing constraints against each other. However, often there is a need for two different versions of a design to be checked against the same timing constraints file or one constraints file against two designs. Constraints Certifier provides a comprehensive capability for checking timing constraints against the design.