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Gencellicon

Constraint Builder

Generate timing constraints from RTL or Netlist. Extract, visualize and analyze design clocking structure and propagation for various modes for any layer of hierarchy. Constraints Builder generates any type of constraints for any mode for various downstream SOC design processes.

Advanced timing constraint capabilities with Excellicon

Acquisition enables SoC designers to accelerate design closure and enhance constraint correctness with management.

Why Constraints Builder?

Constraints builder is the formal constraints compiler tool that automatically generates SDC for any mode and level of hierarchy, shortening the timing closure cycle. Constraints builder automatically compiles, hierarchically propagates and manages sign-off quality correct-by-construction timing constraints for various applications.

Frequently asked questions

The process of generating constraints starts with discovery, where the tool starts at end points, identifies clocks and modes through backward propagation of design layers, allowing designers to visualize clocking structure and determine the modes in the design.