Gencellicon
Clock Analyzer
Clock Analyzer is a clocking logic visualization, analysis and verification tool. Used in pre-CTS clocking analysis and post-CTS clock tree verification, it helps designers to understand clock propagation and topology and merge points to debug clock tree issues, skew groups and any mode conflicts.
Why Clock Analyzer?
Clock Analyzer generates a detailed visual diagram of clocking architecture, clock logic, the clock topology and waveforms, helping the understanding of clock propagation across SOC and the ability to simplify the clocking diagram for easy readability. Designers can explore the clocking logic in determining the clock interactions, clock tree exceptions, skew groups, mode conflicts or other such information.
Analyze pre-CTS clock network
Clock Analyzer helps RTL and implementation engineers with clock design to minimize debug time in understanding the clock network topology. Implementation engineers can define CTS timing constraints to eliminate CTS iterations.
Validate the clock tree early prior to STA
Provides capabilities to check the CTS implementation across power domains, balancing issues, DRC’s, clock tree exceptions, mode conflicts, and validation of any SDC associated with CTS.
Generate efficient skew groups
Analyzing the clock network branches, Clock Analyzer is able to determine and optimize skew grouping of independent branches of clock network to reduce area, power as well as congestion of clock network.
Frequently asked questions
Prior to running automated CTS tools, Clock Analyzer can be used to inspect the clocking architecture and generate a detailed visual diagram of the clock logic, including the clock topology and the associated waveforms, in order to understand the clock propagation across the entire SOC. User can automatically visualize the entire clock network, with flexibility to interactively manage logical and physical hierarchies, combinational logic etc., in order to simplify the clocking diagram for easy readability and documentation. Clock Analyzer can also be used to detect intended or unintended changes in the clock network often encountered during the RTL evolution.