Gencellicon
Chip Planner
Analyze optimum partitioning scenarios of the design based on the designer’s goal. Feasibility analysis of the RTL to eliminate physical issues early on. Estimate PPA at RTL and generate an early floorplan. Generate collaterals for all downstream tools.
Why Chip Planner
Gencellicon Chip Planner is the first shift-left tool enabling designers to gain deep insight into the physical implementation feasibility of their design at very early stages without being dependent on traditional implementation tools. Designers can explore various floorplan scenarios based on identified metrics, with the ability to perform what-if analysis, selecting the most efficient scenario for implementation.
RTL analysis, exploration and partitioning
Chip planner is designed to provide the capability to explore the RTL and suggest various partitioning options based on the chosen criteria. New RTL repartitions will have corresponding SDC generated automatically.
Early RTL floorplanning
Chip Planner provides early insight into physical implementation of design and provides what-if analysis for designers to make the best possible floorplan choices selecting one of many automatically generated floor plans.
Ensure correct design representation
Chip Planner unique floor plan verification allows designers to validate floorplans against actual design description's exhaustive set of rules to check for inconsistencies between the RTL, floorplan, port placement and routing.