Gencellicon software portfolio

Gencellicon is the Siemens EDA timing closure and early design planning suite of products that offering a comprehensive solution that accelerates timing closure across the full spectrum of design activities, including:

1. Timing constraints authoring, compiling, certification, formal validation, and management using multi-mode approach
2. Early design planning in order to predict optimal partitioning scenarios, estimate PPA metrics and to develop early floorplan
3. Pre-CTS and Post-CTS clocking analysis, including generation of CTS guidance file containing clock exceptions and skew group definitions

As SoC designs grow increasingly complex – driven by the integration of more features and tighter PPA requirements – designers face numerous costly and time-consuming iterations to optimize functionality, performance, and manufacturability.

Timing constraints development and validation are critical to every stage of the implementation flow. Designers must create and manage various constraint styles to support different tasks.

Clock design is also becoming increasingly complex with growing chip functionality, requiring substantial effort to analyze, eliminate redundancies, and guide the CTS engine toward an optimal clock tree structure.

The Gencellicon suite addresses key challenges in chip development and timing closure by automating and accelerating the design process. When paired with a shift-left methodology, it enables more predictable and efficient SoC design cycles – reducing cost, schedule, and design iterations. It also facilitates high-quality RTL sign-off, minimizing the risk of rework from synthesis or P&R back to RTL.