Overview
Circuit Design
An analog mixed-signal design flow providing design capture, simulation set-up, launch and results analysis verification.
KEY Features
Custom IC Design Capture
S-Edit increases productivity while handling the most complex IC designs. Once the schematic has been created, the required Analog Mixed simulation runs can be set up, launched, and the results analyzed. Then schematic driven layout can be used to drive the layout process.
Handles your most complex full-custom designs
- Native on OpenAccess
- Multiple-views per cell to support Analog Mixed-Signal Design including: SPICE, schematic, Verilog, Verilog-A, layout, Verilog-AMS, VHDL, and VHDL-AMS views
- Speeds schematic to layout process though SDL and ECO
- Supported by over 180 PDK’s from more than 30 foundries
- Fully scriptable and expandable using TCL/Tk command language
Full featured schematic capture environment
- Advanced array and bus support
- Support for inherited connections
- Compare two schematics and visually displays the differences
- Cross-probe between schematic, layout and Calibre LVS report with net/device highlighting
- Configurable schematic Electrical Rule Checks (ERC)
- Integration with revision control tools
- Available on both Linux and Windows
Simulation setup, launch and results viewing
- Quickly see the pass/fail simulation status of all simulation runs
- Back annotate DC OP simulation results and AC small-signal parameters for devices directly to the schematic
- Multiple testbenches can be defined for different sets of simulation analysis or simulators
- Easily set up sweeps, corners, Monte Carlo and other analyses
- Track and aggregate all simulation measurements for a project
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