An analog mixed-signal design flow providing design capture, simulation set-up, launch and results analysis verification.
S-Edit increases productivity while handling the most complex IC designs. Once the schematic has been created, the required Analog Mixed simulation runs can be set up, launched, and the results analyzed. Then schematic driven layout can be used to drive the layout process.
Native on OpenAccess
Multiple-views per cell to support Analog Mixed-Signal Design including: SPICE, schematic, Verilog, Verilog-A, layout, Verilog-AMS, VHDL, and VHDL-AMS views
Speeds schematic to layout process though SDL and ECO
Supported by over 180 PDK’s from more than 30 foundries
Fully scriptable and expandable using TCL/Tk command language
Advanced array and bus support
Support for inherited connections
Cross-probe between schematic, layout and Calibre LVS report with net/device highlighting
Configurable schematic Electrical Rule Checks (ERC)
Integration with revision control tools
Available on both Linux and Windows
Quickly see the pass/fail simulation status of all simulation runs
Back annotate DC OP simulation results and AC small-signal parameters for devices directly to the schematic
Multiple testbenches can be defined for different sets of simulation analysis or simulators
Easily set up sweeps, corners, Monte Carlo and other analyses
Track and aggregate all simulation measurements for a project
We're standing by to answer your questions.
Get in touch with our sales team 1-800-547-3000 or 1-503-685-8000