Context-aware, scalable, fast and intuitive verification platform for all the functional verification flows across the entire design cycle.
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Today, designs are more complex, with varied components and required analysis such as analog, digital, power, DFT, safety and security. Ensuring the fidelity and robustness of such a design requires verification engineers to plan debug very early. According to the 2022 Wilson research study, design and verification engineers spend 46% of the project time debugging.
Visualizer is the state-of-the-art debug platform suitable for today’s functional verification challenges. With the seamless merging of all advanced debugging features and integration of UVM test benches and Veloce emulation, Visualizer delivers a high-performance debug for block level, IP and full-chip SoCs.
Regardless of whether you are executing in simulation, emulation, or prototyping, Visualizer is the unified debug solution.
Visualizer reads diverse types of verification and design data. Data from design, testbench, assertions, power, software execution and AMS signals can be viewed simultaneously.
Architected to scale with substantial amounts of debug data with the flexibility to zoom in at the unit level or a single network.
Visualizer is one debug platform for all functional verification needs such as HDL, testbench, coverage analysis, power analysis and software debug. Everything useful is in one place and one familiar environment, which improves verification quality and productivity with no new learning required.
As the design sizes and quantity of debug data grows, it is important to consider resource utilization and user experience. Visualizer has been architected to ensure that different methodologies provided with Visualizer do not over-consume the available resources. This optimized resource utilization, means machines with substantial amounts of RAM are not required to use Visualizer.
Visualizer understands the type of data being processed. In addition to providing specialized windows that are specific to power aware flows, all the existing windows, such as source window, schematic window, variable window and waveform window are available to enhance your debug.