Power profiling and analysis
Veloce Power app
Veloce Power app offers power profiling, data generation for power tools, and power-aware verification using Unified Power Format (UPF) at SoC level. It supports complete power analysis across design flows, including RTL and netlist emulation, plus RTL emulation with netlist-based power analysis.
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Why the Veloce Power app?
Veloce Power app generates precise power profiles by analyzing the design under realistic workloads and test scenarios, leveraging standard libraries. Profiling can be targeted to specific IPs and subcomponents with results broken down into register, clock, memory and combinational power trends. These profiles support power trend analysis and peak detection.
Additionally, a logical heatmap is generated which can indicate the power density at any given time in simulation. The power trend has a high correlation with sign-off power tools. Since the Veloce platform has full internal visibility, enabling power profiling requires no additional emulation capacity to achieve full accuracy.
The flow is available for both register-transfer level (RTL) and gate-level netlist designs. For deep analysis, the power trend analysis graphic-user interface (GUI) enables various dashboards such as energy trend, power trend, and register toggle ratio (percentage of Q toggles vs total number of registers). Features like time zone identification and selection let the user identify areas of interest for further analysis and to generate time zone files for stimulus generation and power tools.
Key Features:
- Generates power trends for both RTL and netlist in the context of realistic workloads and identifies peak power periods.
- Generate streaming data for application program-interface (API) / fast-signal database (FSDB) / or switching activity interchange format (SAIF) for power tools for and full SoC power aware verification with unified power format (UPF).
- Automatically extracts state and state transition coverage metrics to identify gaps and develop additional scenarios to close them.
- Built-in static and dynamic assertions detect issues early, and advanced debug tools (such as corruption disabling and x-aware waveform dumps) simplify debugging across hardware and software layers.
Power profiles align with user proven silicon trends
Delivers power profiles that closely correlate with post-silicon power trends. Validated across many designs, ensuring confidence in early power analysis and architecture-level decision making.
Understanding power profile for real workloads
Gain early visibility into power profiles under real workloads to identify hot spots, reduce overdesign, and make informed data driven decisions that prevent power-related issues late in the design cycle.
Generation of data for power tools at RTL and netlist
Supports Power data generation at RTL for fast insights, and at netlist for DFT patterns and higher accuracy. At netlist, no mapping file is needed—removing a key challenge when proving power at the SoC level.
Key attributes
Data generation for power tools
Veloce Power App provides file-based outputs for cycle-accurate power analysis using Fast-Signal Database (FSDB) / and for average power using Switching Activity Interchange Format (SAIF). Streaming APIs also reduce disk usage and processing time by providing only essential data to downstream power tools.
Power-aware verification with UPF
Full SoC emulation with Unified Power Format (UPF) finds power-related issues typically missed in simulation, especially under long tests and realistic workloads. Veloce Power App instruments power-aware logic automatically and supports both on-chip and off-chip power management controllers.
Coverage for power-aware verification
Like functional verification, power-aware verification relies on comprehensive coverage. Veloce Power App automatically extracts state and state transition coverage metrics, helping users identify gaps and develop additional scenarios to close them.
