Whether you are running a traditional structural test, memory built-in self-test (MBIST) or more advanced design for test (DFT), formats like Parametric, I/O characterization and even functional test, the Veloce DFT App can handle all of the various DFT test modes that are run on production SoCs
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Veloce Design-for-Test (DFT) App provides a shift-left approach to design for test pattern validation. The Veloce DFT App is an emulation-optimized DFT pattern validation flow that is faster than traditional software simulation. The DFT App is compatible with all of the various types of test patterns that run on the ATE (automated test equipment). The Veloce DFT App is fully compatible with the Veloce Fault App to accurately measure fault coverage or provide a functional fault grading metric. It is used in conjunction with the Veloce Power App, power profiling and estimation of the pattern to ensure a highly robust production program.
Efficiently handle netlist or register-transfer level (RTL) at full-chip System-on-Chip (SoC) for design sizes up to 40B gates.
Veloce DFT outperforms traditional simulation by orders of magnitude. In some cases as much as 16K times the performance
Veloce DFT App supports industry-wide Standard Test Interface Language (STIL) file format
The number of test patterns that must be run to fully validate a SoC costs time and money. These large pattern sets must be robust and working during first silicon, so they do not jeopardize the production delivery schedule. With Veloce DFT App and emulation-based acceleration of upwards of 10K times faster than software simulation, a more formal validation process can be established to achieve targeted goals.
With Veloce DFT a structural analysis of the design is executed to root out coverage holes in the production program. Once this set of faults is found, and a stimuli is created, the Veloce DFT and Fault Apps completely automate the process of running the test and injecting the faults in an iterative fashion. The resultant fault coverage can be merged with ATPG coverage database for final test program coverage.
Structural DFT test methods add extra nonfunctional test-only logic into the design, where power nets and layout of the design may not be optimized for this extra logic leading to power, temperature, and speed events at tests that can reduce yields and impact project revenue. The Veloce DFT App along with the Veloce Power App can give an insight into power events and estimations early in design and planning.