Design for test
Veloce DFT App
Whether you are running a traditional structural test, memory built-in self-test (MBIST) or more advanced design for test (DFT), formats like Parametric, I/O characterization and even functional test, the Veloce DFT App can handle all of the various DFT test modes that are run on production SoCs
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Why the Veloce DFT App?
Veloce Design-for-Test (DFT) App provides a shift-left approach to design for test pattern validation. The Veloce DFT App is an emulation-optimized DFT pattern validation flow that is faster than traditional software simulation. The DFT App is compatible with all of the various types of test patterns that run on the ATE (automated test equipment). The Veloce DFT App is fully compatible with the Veloce Fault App to accurately measure fault coverage or provide a functional fault grading metric. It is used in conjunction with the Veloce Power App, power profiling and estimation of the pattern to ensure a highly robust production program.
- Validate all patterns for correctness before shipping to production
- Standard Test Interface Language (STIL)
- Support all patterns that run on ATE tester
- DFT App is optimized for emulation
- Takes advantage of Co-model streaming bandwidth
- Increase fault coverage through the use of the Veloce Fault App
- Power profiling and estimation of patterns through the use of the Veloce Power App
- Reduce sim time
Designed to meet the challenges of DFT validation
Efficiently handle netlist or register-transfer level (RTL) at full-chip System-on-Chip (SoC) for design sizes up to 40B gates.
Support for the most common ATE file types
Veloce DFT App supports Standard Test Interface Language (STIL) file format.
Achieve acceleration
Veloce DFT outperforms traditional simulation.
Key attributes
DFT pattern validation
The number of test patterns that must be run to validate a SoC fully costs time and money. These large pattern sets must be robust and working during the first silicon so they do not jeopardize the production delivery schedule. With Veloce DFT App and emulation-based acceleration faster than software simulation, a more formal validation process can be established to achieve targeted goals.
Functional fault grading
With Veloce DFT, a structural analysis of the design is executed to root out coverage holes in the program. Once this set of faults is found and a set of stimuli is created, the Veloce DFT and Fault App completely automate the process of running the test and injecting the faults in an iterative fashion. The resultant fault coverage can be merged with ATPG coverage database for final test program coverage.
Power estimation and analysis
Structural DFT test methods add extra nonfunctional test-only logic into the design, where power nets and layout may not be optimized for this extra logic, leading to power, temperature and speed events at tests that can reduce yields and impact project revenue. The Veloce DFT App, along with the Veloce Power App, can give an insight into power events and estimations early in design and planning.
