To keep up with an ever-evolving industry, companies must be able to quickly verify a design’s ability to meet specification and compliance goals. The Veloce Coverage and Assertion app accelerates debug times by ensuring coverage closure during testing.
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The Veloce Coverage and Assertion app provides extensive analysis of testing efforts, and when combined with metric-driven verification techniques, highlights early issues that may become critical flaws in later phases. By ensuring the completeness of design verification, the likelihood of first-pass silicon success increases drastically:
Use coverage analysis to optimize verification plans and guarantee thorough design testing.
Seamlessly transfer and merge coverage and assertions between simulation and emulation stages of verification.
Coverage can be activated and deactivated for different levels of the design, allowing for focus on specific aspects of testing.
The Veloce Coverage and Assertion app enables code coverage that analyzes code execution, and functional coverage and tracks user-defined specification execution. By achieving high levels in these metrics, a thorough level of testing can be ensured.
For testbenches that do not have built-in monitors or checkers, assertions can be used with the Coverage and Assertion app tracking the number of times they fire. As well, assertion-based triggers can be used to enable behaviors when fired, such as waveform generation or test execution.
The Coverage and Assertion app provides the ability to not only activate and deactivate coverage, but merge coverage as well. This provides the ability to combine any previously collected together to have a more holistic view of
verification. Coverage collected from both Questa and Veloce can be merged
together as well.
The Coverage and Assertion app can be combined with other Siemens EDA tools to ensure complete testing of specific design aspects. For example, the app can be combined with the Veloce Power app to create targeted workloads for system and sub-system power testing.