Quickly prove that a design is functionally identical—compare RTL to gate netlist for synthesis, gate-to-gate netlists for layout spins, and RTL-to-RTL for language conversion. Use one tool and flow for all your designs.
Rapid verification of multi-million gate designs and dramatic reduction in verification time using static formal verification techniques. Fastest route to correct design with a comprehensive debug tool that identifies the location/cause of errors and the unique “what-if” capability to investigate design modifications within the existing verification session.
FormalPro and Precision Synthesis provide unique integration for equivalence checking of FPGAs. An FVI setup file, containing synthesis optimization information, is auto-generated by Precision, enabling a reliable push-button RTL to gate netlist equivalence checking. Xilinx and Microchip (Microsemi) FPGA devices are supported in this flow.
Incremental changes are common for today’s complex designs. The verification restart feature reduces verification time further by eliminating the need to recompile and rerun the entire verification with each incremental design and setup change—it recompiles only the design that has changed. Additionally, you may restart at any intermediate point.
Join the discussion on new topics, features, content, and technical experts.
Access detailed user application notes, training resources and more.
Helping you achieve maximum business impact by addressing your complex technology and enterprise challenges with a unique blend of development experience, design knowledge, and methodology expertise.