FormalPro uses static formal verification techniques to prove that a design is functionally identical to its golden reference. This is orders of magnitude faster than traditional gate-level simulation - designs that take days or weeks can be verified in hours or even minutes using FormalPro.
Quickly prove that a design is functionally identical - compare RTL to gate netlist for synthesis, gate to gate netlists for layout spins. Use one tool and flow for all your designs.
Rapid verification of multi-million gate designs and dramatic reduction in verification time using static formal verification techniques. Fastest route to correct design with a comprehensive debug tool that identifies the location/cause of errors and the unique “what-if” capability to investigate design modifications within the existing verification session.
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