Overview
Calibre LSG
Calibre LSG can generate quality and comprehensive layout to collect silicon test chip measurements, discover lithographic hotspots and probe design/process interaction effectively. Calibre LSG can also be used to design targeted density gradients to uncover CMP limitations.
Get in touch with our technical team 1-800-547-3000
Guided-random synthetic layout generation
Calibre LSG creates product-like DRC-clean layout and/or complex layout to stress DR corners, delivers layouts for engineering teams to test for their solutions, and enables cross-company/cross-team collaboration through sharing synthetic test cases free of proprietary IP constraints.
Accelerate early process node development and DTCO
Calibre LSG provides user configurable guided-random layout generation to produce DRC-clean design fabrics for optical and electrical test chip development. Calibre LSG shortens the loop of building test chips for silicon measurements and drives process improvement faster.
PDK development and quality assurance
Calibre LSG can be used for quality DRC rule deck development and PDK improvements. Calibre LSG can generate DRC-clean layout, layouts that stress DR corner combinations, as well as layouts with deliberately injected DR violations to verify DRC rule deck quality and completeness.
Enable early machine learning training
Calibre LSG provides layouts containing real lithography hotspot information for machine learning training when real design data is unavailable. The ML training datasets can be enriched by improving layout space coverage using Calibre LSG, and accurate ML engine can be trained for EDA ML applications for hotspot prediction early in development cycle.
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Call: 1-800-547-3000
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Across all process nodes and design styles, the Calibre toolsuite delivers accurate, efficient, comprehensive IC verification and optimization, while minimizing resource usage and tapeout schedules.