Overview

Calibre nmDRC

Accelerate tapeout with faster verification. As designs grow and errors rise, Calibre nmDRC cuts total cycle time with advanced capabilities that go beyond traditional design rule checking.

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Key Features

Industry-Leading Sign-Off Design Rule Checking

The Calibre nmDRC platform has been adopted as the internal sign-off design rule checking solution for all major foundries for over 25 years, due to its continuous innovation in functionality to meet the most complex rule needs, as well as its industry-leading performance and capacity.

Accuracy and Innovation

Preferred Foundry Sign-Off Tool

The Calibre nmDRC technology is used internally by all major foundries for process definition, resulting in rule files and rule decks that define the process requirements and set the benchmark for other companies’ design rule checking tool qualifications.

Man shaking hands with electronic hand | The Calibre nmDRC technology is used internally by all major foundries for process definition, resulting in rule files and rule decks that define the process requirements and set the benchmark for other companies’ DRC tool qualifications.
Most Advanced Syntaxes

Constant Innovation

With innovative features like equation-based design rule checking and other advanced syntaxes, the Calibre nmDRC solution enables the implementation of complex new check requirements without requiring underlying engine modification.

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Fastest runtimes

Industry leading performance and capacity

The Calibre nmDRC hierarchical processing engine continues to set the industry benchmark for performance, scaling, and capacity. Extended with industry-leading scaling technology, the Calibre nmDRC platform enables the fastest runtimes with low memory and core counts.

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Calibre nmDRC featured resources

Explore our featured resources or visit the full Calibre nmDRC resource library to view on-demand webinars, white papers, and fact sheets.

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Calibre consulting services

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Design with Calibre blog

The Calibre tool suite delivers accurate, efficient, comprehensive IC verification and optimization across all process nodes and design styles while minimizing resource usage and tapeout schedules.