Planarity variation creates hotspots that impact both chip manufacturability and the electrical performance of the design. The Calibre CMPAnalyzer tool examines a layout and simulates the thickness of each layer to enable designers to intelligently modify the design to reduce variation effects.
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The Calibre CMPAnalyzer tool lets designers use simulation results to visually highlight and examine a variety of CMP effects. Designers can examine these results layer by layer, and for selected areas in the layout. They can also review specified CMP hotspot checks, such as depth of focus checks.
Visualization of impacts
Data provided by CMP simulators to the Calibre CMPAnalyzer tool enable designers to visually highlight and examine a variety of CMP effects. Designers can examine these results layer by layer, and for selected areas in the layout. They can also review specified CMP hotspot checks, such as depth of focus checks.
Using thickness simulation data from the simulator, the Calibre CMPAnalyzer tool determines the optimum filling strategy and passes the information to the Calibre YieldEnhancer tool. The combination of accurate simulation data and the innovative Calibre fill algorithm improves parametric yield while minimizing the added capacitance.
Improved timing validation
The Calibre CMPAnalyzer tool integrates with Calibre xRC parasitic extraction to create a comprehensive 3D model of the interconnect parameters that more closely matches silicon results. The Calibre xRC tool accurately accounts for the thickness variation across the design, letting designers use this information to validate timing.
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