The Calibre xRC tool provides robust parasitic extraction that delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation. The result is compact, hierarchical, transistor-level parasitic data that can be back-annotated and simulated.
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Calibre xRC parasitic extraction enables seamless creation of netlists and parasitic debugging in the design environment. The flexible data model supports diverse design flows and styles, including analog, memory, ASIC, and mixed signal. Foundry-qualified for virtually all processes and nodes.
Advanced extraction and process models correlate closely with field solver results; proprietary reduction algorithm maintains integrity of parasitic data. Reduces need for prohibitive design margins by incorporating manufacturing-dependent effects (e.g., in-die variation) into parasitic models.
The Calibre xRC tools exchange native database information with Calibre nmLVS, Calibre PERC, and Calibre xACT 3D products. Upstream design integration using Calibre interfaces enables GUI-driven launch, back annotation, and cross-probing for all popular layout environments. Fully compatible with downstream digital, custom, and mixed-signal flows.
Combines the performance of the Calibre hierarchical and multi-threaded architecture with a compact netlist to boost throughput of large designs and maintain rapid feedback within custom design environments. Multiple process corner analysis does not require complete design re-run.
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Across all process nodes and design styles, the Calibre toolsuite delivers accurate, efficient, comprehensive IC verification and optimization, while minimizing resource usage and tapeout schedules.