{"showBreadcrumbs":true,"breadcrumbs":[{"title":"Siemens EDA Software","path":"/en-US/"},{"title":"IC Tool Portfolio","path":"/en-US/ic"},{"title":"Calibre Design Solutions","path":"/en-US/ic/calibre-design"},{"title":"Circuit Verification","path":"/en-US/ic/calibre-design/circuit-verification"},{"title":"Calibre xRC","path":""}],"tagline":"Overview","title":"Calibre xRC Extraction","description":"The Calibre xRC tool provides robust parasitic extraction that delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation. The result is compact, hierarchical, transistor-level parasitic data that can be back-annotated and simulated.","pricingCurrency":"US$","image":{"url":"//images.ctfassets.net/17si5cpawjzf/mEBc5lfWTCtUYMwJZy4Yt/54a1bc4f94210c364f51a3a89053eba1/calibre-xrc-top-is1090011368-640x480.jpg?w=640","alt":"Blue waves of discrete dots | The Calibre xRC tool provides robust parasitic extraction and accurate parasitic data for comprehensive and accurate post-layout analysis and simulation.","linkData":"{\"name\":\"calibre-xrc-top-is1090011368-640x480\",\"id\":\"mEBc5lfWTCtUYMwJZy4Yt\",\"contentType\":\"image/jpeg\"}"},"secondaryButton":{"text":"Read White Paper","resource":{"ids":["6BJnQR8SL2JIFEWmwt2kDN"],"mode":"selected","query":{"q":"Validating rule-based parasitic extraction against a field solver","sorts":[{"field":"publishedDate","order":"desc"}],"filters":[{"field":"collection","values":["resource"],"operator":"OR"}],"postFilters":[],"verboseLocalization":true},"idsQuery":{"size":1,"filters":[{"field":"collection","values":["resource"],"operator":"OR"},{"field":"id","values":["6BJnQR8SL2JIFEWmwt2kDN"],"operator":"OR"}],"verboseLocalization":true}},"env":"master"},"phoneIcon":true,"moreInformation":"Get in touch with our technical team 1-800-547-3000"}
Overview

Calibre xRC Extraction

The Calibre xRC tool provides robust parasitic extraction that delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation. The result is compact, hierarchical, transistor-level parasitic data that can be back-annotated and simulated.


Get in touch with our technical team 1-800-547-3000

Blue waves of discrete dots | The Calibre xRC tool provides robust parasitic extraction and accurate parasitic data for comprehensive and accurate post-layout analysis and simulation.

Calibre xRC Resources

Key Features

Performance and Accuracy for All Designs and Nodes

Calibre xRC parasitic extraction enables seamless creation of netlists and parasitic debugging in the design environment. The flexible data model supports diverse design flows and styles, including analog, memory, ASIC, and mixed signal. Foundry-qualified for virtually all processes and nodes.

Industry-Proven Accuracy

High-Performance Rule-Based Parasitic Extraction

Advanced extraction and process models correlate closely with field solver results; proprietary reduction algorithm maintains integrity of parasitic data. Reduces need for prohibitive design margins by incorporating manufacturing-dependent effects (e.g., in-die variation) into parasitic models.

Indistinct background of pastel dots behind a blurred grid | Calibre xRC advanced extraction and process models correlate closely with field solver results; proprietary reduction algorithm maintains integrity of parasitic data. Reduces need for prohibitive design margins by incorporating manufacturing-dependent effects (e.g., in-die variation) into parasitic models.

Easy Flow Integration

Integrated Calibre Verification Flow

The Calibre xRC tools exchange native database information with Calibre nmLVS, Calibre PERC, and Calibre xACT 3D products. Upstream design integration using Calibre interfaces enables GUI-driven launch, back annotation, and cross-probing for all popular layout environments. Fully compatible with downstream digital, custom, and mixed-signal flows.

puzzle with last piece going into place | The Calibre Pattern Matching tool works within the Calibre platform to enable powerful integrated pattern-based design verification and manufacturing flows.

Boost throughput

Full-chip performance

Combines the performance of the Calibre hierarchical and multi-threaded architecture with a compact netlist to boost throughput of large designs and maintain rapid feedback within custom design environments. Multiple process corner analysis does not require complete design re-run.

chips on board with connections transmitting signals | The Calibre DESIGNrev FileMerge functionality supports a variety of chip assembly and editing flows to create full-chip layouts ready for sign-off verification without the heavy hardware requirements of traditional design tools.

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Call: 1-800-547-3000

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We help you adopt, deploy, customize, and optimize your complex design environments. Direct access to engineering and product development lets us tap into deep domain and subject matter expertise.

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Design with Calibre Blog

Across all process nodes and design styles, the Calibre toolsuite delivers accurate, efficient, comprehensive IC verification and optimization, while minimizing resource usage and tapeout schedules.

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