The Calibre xRC tool provides robust parasitic extraction that delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation. The result is compact, hierarchical, transistor-level parasitic data that can be back-annotated and simulated.
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Foundries and EDA vendors must ensure that their PEX rule decks provide accurate extraction. Design companies must ensure the accuracy of their rule-based PEX tool. Correlating rule-based PEX results against a field solver extraction provides reference numbers they can trust, as long as they set up the runs properly to ensure an “apples to apples” comparison.
Calibre xRC parasitic extraction enables seamless creation of netlists and parasitic debugging in the design environment. The flexible data model supports diverse design flows and styles, including analog, memory, ASIC, and mixed signal. Foundry-qualified for virtually all processes and nodes.
Excellent correlation with field solver results; proprietary reduction algorithm maintains integrity of parasitic data. Models incorporate manufacturing-dependent effects to reduce the need for prohibitive design margins.
Exchanges native database information between Calibre products. Integrated with Calibre interfaces for GUI-driven launch, back annotation, and cross-probing for all popular layout environments and compatible downstream flows.
Boosts throughput of large designs and feedback within custom design environments with the Calibre hierarchical, multi-threaded architecture and a compact netlist. Multiple process corner analysis does not require full re-run.
The parasitic elements are the unintended passive elements, such as capacitor, resistor, and inductor, that do not exist in the circuit design but exist in the final chip.
Layout Parasitic extraction (LPE) is the process of calculating the interconnect parasitic elements, such as parasitic capacitance, resistance, and inductance of metal interconnect wires. These parasitic effects arise due to the non-ideal behavior of the stack metallization, for example, interconnect wires, transistors, and other components. Such parasitic elements can significantly impact the performance and reliability of a chip.
As integrated circuits (ICs) become more complex, designers face increasing challenges in ensuring accurate and reliable operation. One critical aspect of this is handling the parasitic elements. Without accurate layout parasitic extraction, designers’ risk poor performance, increased power consumption, and even catastrophic failure. By accounting for parasitic effects during the design process, engineers can optimize circuit performance and minimize the risk of costly errors. Parasitic extraction is an essential tool in modern IC design, enabling engineers to create chips that operate efficiently and reliably in a wide range of applications.
A Rule based layout parasitic extraction is a parasitic extraction method that relies on a pre characterized library of parasitic models (e.g., formulas) that are used to calculate parasitic elements. Rule-based parasitic extraction tools are widely used by circuit designers because they are fast, provide reasonable accuracy, and have high capacity. Moreover, rule-based engines are faster than FS for full chip parasitic extraction.
Calibre xRC is a sign-off layout parasitic extraction tool by Siemens EDA. Calibre xRC is a fast and accurate layout parasitic extraction tool with high capacity. Calibre xRC is qualified on a wide range of process technology nodes across many foundries.
An input layout that describes the physical design represented as geometry is needed, this layout design must be DRC & LVS clean. Calibre xRC also needs extraction rules & LVS rules that are qualified by the foundry for the corresponding technology.
A rule based engine has pre characterized models to extract the parasitic component. Rule-based engines are fast, provide reasonable accuracy, and have high capacity. They are faster than field solvers and can handle full chip parasitic extraction.
A field solver is electrostatic (or electromagnetic) simulation software for accurately calculating and analyzing the behavior of electric fields and electromagnetic waves on an integrated circuit. Rather than relying on simplified models or theoretical calculations, a field solver uses advanced numerical methods to simulate 3D interactions between electric charges, currents, and materials.
Field solver could be used for sensitive RF application and STD cells / Memory cells characterization.
As for xRC (Calibre’s rule-based engine) is the targeted engine for mature nodes (20nm and above) and regular devices (MOSFET, BJT...)
Yes, through Calibre interactive (GUI). You can easily select specified nets either to include or exclude in your extraction, Calibre xACT3D can use the same rules deck as Calibre xRC.
Calibre xRC is a rule-based engine that is qualified for mature nodes (20nm and above).
Calibre xACT is a hybrid engine between rule-based engine and field solver, it is designed to handle the complexity in devices for advanced nodes.
It depends on the technology node; in this case it’s better to consult with the foundry to point you to the qualified tool for the desired technology node.
Yes, Calibre xRC has many reduction algorithms built in, including frequency-based reduction, threshold-based reduction, via reduction, and metal fill reduction.
Calibre xRC doesn’t support digital / LEFDEF designs extraction. Users can still run Calibre xACT for digital / LEFDEF designs using the standard xRC foundry qualified decks.
Yes, you can specify the parasitics you wish to extract. Either capacitance only, resistance only or both resistance and capacitance. In addition to the inductance which can be either self-inductance only or self and mutual inductance extraction.
Yes, Calibre xRC is integrated intodifferent design platforms. Starting the run uses Calibre Interactive GUI, and debugging the parasitics is done with Calibre RVE, which allows parasitics to be highlighted on the layout. The parasitic output is in Calibre view format, which is a graphical extracted view.
Point to point resistance is a good utility to measure resistance between two points interactively from the layout after parasitic extraction, this helps to identify routes with high resistance so that designer would tweak the design to avoid them accordingly.
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