Overview

Calibre nmLVS

The Calibre nmLVS platform is the market leader in IC layout vs. schematic circuit verification, delivering production-proven device and connectivity extraction for both physical verification and parasitic extraction.


Get in touch with our technical team 1-800-547-3000

Improving productivity with more efficient LVS debug

Calibre RVE utilities help designers debug and fix LVS errors more quickly, while also eliminating the need for multiple full LVS runs. Interactive short isolation provides a systematic and prioritized shorts debugging process. Fix suggestions in plain text help designers find the root cause of LVS comparison discrepancies, while the ability to highlight discrepancies in both layout and schematic views lets them implement fixes quickly and efficiently.

Improving productivity with more efficient LVS debug
Key Features

Production-Proven, Trusted Circuit Verification

The Calibre nmLVS platform is trusted by designers, engineers, and management for its proven performance, capacity, reliability, and debug ease-of-use. Accurate and precise circuit verification is an essential component of world-class silicon delivery.

Sets the Benchmark

Flexibility and Predictability

The Calibre nmLVS platform is ideally suited for processing any size job requiring intricate device parameter extraction, whether they’re analog/RF designs or multimillion gate ICs. Preferred by all major foundries, the Calibre nmLVS tool sets the benchmark for LVS accuracy, reliability, and predictability.

wooden puzzle pieces fitting together | The Calibre nmLVS platform is ideally suited for processing any size job requiring intricate device parameter extraction, whether they’re analog/RF designs or multimillion gate ICs. Preferred by all major foundries, the Calibre nmLVS tool sets the benchmark for LVS accuracy, reliability, and predictability.
Intuitive and Easy to Use

Design Debugging and Ease-of-Use

The Calibre nmLVS platform provides an intuitive and easy-to-use integrated design verification debugging environment to help you quickly find and fix design issues. Calibre nmLVS runtimes are typically 2-3x faster than traditional layout vs. schematic processes.

Red ball rolling through a maze | The Calibre nmLVS platform provides an intuitive and easy-to-use integrated design verification debugging environment to help you quickly find and fix design issues. Calibre nmLVS runtimes are typically 2-3x faster than traditional layout vs. schematic processes.
Fast Runtimes

Best-in-Class Accuracy and Runtime

The Calibre nmLVS platform delivers the trusted device recognition accuracy and timely execution IC design companies and foundries require, while innovative hierarchical and logic injection technologies provide virtually unlimited design scope with fast runtimes.

Dart hitting the bullseye on target | The Calibre nmLVS platform delivers the trusted device recognition accuracy and timely execution IC design companies and foundries require, while innovative hierarchical and logic injection technologies provide virtually unlimited design scope with fast runtimes.

Calibre nmLVS Featured Resources

Explore our featured resources or visit the full Calibre nmLVS resource library to view on-demand webinars, white papers, and fact sheets.

Ready to learn more about Calibre?

We're standing by to answer your questions! Get in touch with our team today:

Call: 1-800-547-3000

Send an email

Calibre consulting services

We help you adopt, deploy, customize and optimize your complex design environments. Direct access to engineering and product development lets us tap into deep domain and subject matter expertise.

Support center

The Siemens Support Center provides you with everything in one easy-to-use location -
knowledgebase, product updates, documentation, support cases, license/order information and more.

Design with Calibre blog

Across all process nodes and design styles, the Calibre tool suite delivers accurate, efficient, comprehensive IC verification and optimization, while minimizing resource usage and tapeout schedules.