IC implementation solution
Aprisa SoC Design Software
Designing at advanced process nodes requires a new place-and-route paradigm to manage the increasing complexity. Aprisa is a detail-route-centric physical design platform for the modern SoC.
Accelerate SoC design with place-and-route technology
Aprisa digital implementation is an RTL2GDSII solution that offers complete synthesis and place-and-route functionality for top-level hierarchical designs and block-level implementation. It's tapeout quality correlation with signoff tools, both for STA timing and DRC, reduces design closure and ensures optimal performance, power and area (PPA).
Benefits of using Aprisa SoC design software?
Aprisa delivers optimal PPA out-of-the-box. This helps physical designers reduce the effort at each step of the place-and-route flow and achieve faster time-to-market
Fast design closure
Unified architecture and common analysis engines ensure excellent timing and DRC correlation between implementation steps and with signoff tools, greatly reducing the number of flow iterations and ECOs
AI technologies to aid designers on tasks
AI-driven Auto Macro Placement (AMP) technology delivers expert designer quality macro placement at a fraction of the time
Unmatched out-of-the-box PPA
Aprisa's detail-route-centric architecture delivers excellent out-of-the-box results through reference flows that eliminate the need for place groups or margins during placement and CTS
Best cost-of-ownership
Certified at the most advanced nodes by the main Foundries,
while supporting mature nodes. Aprisa is the easiest digital implementation solution to adopt and the most efficient for both engineering and computing resources
Place-and-route for complex SoC designs
Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. Its detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results (QoR) at a competitive runtime.
Reduced time-to-design closure
A unified data model brings real route information and parasitics to any engine and step in the flow. Designers can confidently know their design's achievable PPA at pre-route stage, greatly reducing full-flow iterations
AI-driven macro placement technology
Expert designer quality macro placement at a fraction of the time and effort that it would take an experienced designer. Eliminates the need for full-flow iterations to lock down the optimal macro placement for a given design
Low power patented technology
Target low power as a primary design metric for power sensitive designs, without sacrificing performance. Designers choose the tradeoffs that meet their optimal PPA, reducing power cleanup on the last mile of the design tapeout
Aprisa resource library
Whether physical designers are looking to implement highly complex designs or to tapeout in the shortest amount of time, Aprisa operates mostly out-of-the-box to deliver the PPA and design metrics that matter most, for any given digital IC design project.
