osmosis 2025 conference

9:30 a.m. -
10 a.m.

Registration and Check-in

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10 a.m. -
10:05 a.m.

Welcome and Introduction

Presenter: Nidhi Jain, Functional Verification

10:05 a.m. -
10:45 a.m.

Revolutionizing Chip Development with AI & Next-Gen Verification Solutions

Presenter: Abhi Kolpekwar - Siemens EDA

10:45 a.m. -
11:20 a.m.

Automated Trust and Assurance for ASIC and FPGA Designs: Mitigating Security Risks with Formal Verification

Presenter: Mitchell Poplingher, Lockheed Martin

11:20 a.m. -
11:55 a.m.

Rapid Retargeting of Formal Connectivity Verification of AI FPGA Systems

Presenter: Benjamin Ting, Microsoft

Noon -
1 p.m.

Lunch and Networking

1 p.m. -
1:35 p.m.

Tackling Formal Verification of Larger Designs Using a Modular Approach

Presenter: Ratish Punnoose, Sandia National Labs

1:35 p.m. -
2:10 p.m.

SLEC Flow: Leveraging Formal in Math Primitive Verification Closure

Presenters: Abhiram Dronavalli, Microsoft; Suda Raman, Microsoft

2:10 p.m. -
3 p.m.

The Formal Promise Realized: Why now is the time for formal in the mainstream

Presenter: Chris Giles, Siemens EDA

3 p.m. -
3:30 p.m.

Ask the Experts Panel

Closing Remarks