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Calibre Manufacturing at SPIE Advanced Lithography 2025
Join us at the SPIE Advanced Lithography conference 2025 at the San Jose Convention Center.
Exhibition dates/times
- Feb. 25: 10 a.m. – 5 p.m.
- Feb. 26: 10 a.m. – 4 p.m.
Visit us at Booth #307
If you need assistance outside of booth hours, email us with questions.
“We are pleased to once again collaborate with SPIE to award the seventh annual Nick Cobb Memorial Scholarship to Mr. Clay Klein. The scholarship honors Nick's pioneering work in the field of lithography and his significant contributions as the chief architect of the Siemens EDA Calibre OPC solutions. It is particularly noteworthy that Clay is pursuing his PhD at the same school where Nick completed his undergraduate education, the University of Colorado at Boulder. We are proud to continue this legacy of fostering innovation and engineering talent, especially as Clay's research on EUV metrology is highly relevant to addressing our industry's challenges at advanced nodes."
YuYang Sun, Vice President of Product Management for Siemens EDA's Calibre Semiconductor Manufacturing Solutions.
Calibre IC Manufacturing papers at SPIE 2025
Join Calibre IC Manufacturing at SPIE Advanced Lithography 2025, Feb. 23 - 27, at the San Jose Convention Center. Siemens will be presenting 16 papers. (All presentations are listed in Pacific Time.)
Feb. 25, 2025 • 12:10 p.m. - 12:30 p.m.
A study on the improvement of machine leaning (ML)-based defect prediction model reflecting process variations (Invited Paper)
Paper 13425-4
Feb. 25, 2025 • 3:00 p.m. - 3:20 p.m.
Guided random synthetic layout generation and machine-learning based defect prediction for leading edge technology node development (Invited Paper)
Paper 13425-8
Feb. 25, 2025 • 3:00 p.m. - 3:20 p.m.
Resolution enhancement for high-NA extreme ultraviolet lithography using aperiodic multilayer masks
Paper 13424-22
Feb. 26, 2025 • 9:20 a.m. - 9:40 a.m.
Enablement of 0.55NA EUV bright field mask stitching
Paper 13424-29
Feb. 26, 2025 • 12:10 p.m. - 12:30 p.m.
Enhancing multi-layer process defect prediction accuracy on an Artificial Intelligence/Machine Learning (AI/ML) platform
Paper 13425-22
Feb. 26, 2025 • 1:40 p.m. - 2:00 p.m.
A comparison of SALELE with traditional lithography and anti-spacer technology (Invited Paper)
Paper 13425-23
Feb. 26, 2025 • 5:30 p.m. - 7:00 p.m.
An improved ridge extraction algorithm for the development of lithographic masks
Paper 13426-148
Feb. 26, 2025 • 5:30 p.m. - 7:00 p.m.
Optimizing EUV OPC runtime and pattern fidelity in DRAM manufacturing using memory OPC flow
Paper 13427-66
Feb. 26, 2025 • 5:30 p.m. - 7:00 p.m.
LCDU enhancement of 2D array layouts through curvilinear solutions for DRAM DUV critical layers
Paper 13424-57
Feb. 26, 2025 • 5:30 p.m. - 7:00 p.m.
Machine-learning based etch retarget for Manhattan and curvilinear designs
Paper 13425-57
Feb. 26, 2025 • 5:30 p.m. - 7:00 p.m.
End-to-end automated data cleaning, pattern fidelity assessment, line edge roughness evaluation, and defect detection on SEM images of silicon wafers: a novel machine learning and image processing approach
Paper 13426-112
Feb. 26, 2025 • 5:30 p.m. - 7:00 p.m.
Quantitively metrology for anti-spacer patterning process development
Paper 13426-122
Feb. 27, 2025 • 8:00 a.m. - 8:20 a.m.
OPC model accuracy of dry resist readiness for 0.55NA EUVL by using low-n bright field mask (Invited Paper)
Paper 13425-33
Feb. 27, 2025 • 9:20 a.m. - 9:40 a.m.
Noble methodology generating process proximity correction model utilizing AI based clustering and SEM contour
Paper 13425-37
Feb. 27, 2025 • 11:00 a.m. - 11:20 a.m.
Chemical stochastic variability in compact stochastic e-beam mask writing and EUV lithography models
Paper 13428-60
Feb. 27, 2025 • 1:50 p.m. - 2:10 p.m.
Exploiting machine learning clustering methods to optimize OPC model
Paper 13425-43