Improve the fidelity of ESD margins and leakage flows

Conservative design rules and constraints are often used in reliability verification flows. By combining the leading solutions provided by Siemens Calibre PERC and SPICE simulation technologies, SPICE-accurate full-chip simulation becomes possible in a compelling flow for design teams looking to better understand their ESD design margins. For analog designers, we will explore exciting challenges and verification developments to minimize IC circuit leakage in your designs.

Join the presenters from Silicon Labs and Siemens as we demonstrate the benefits provided by the compelling technologies of Siemens Calibre PERC and SPICE simulation technologies provide when exercised in unison. This lunchtime DAC session includes:

• Exploration of the compelling technology that improves the fidelity of results to better understand ESD design margins.
• Perform full-chip SPICE-accurate simulations on ESD paths within your design.
• Learn about new technology helping analog IC and custom digital designers tackle design leakage challenges.