Siemens EDA events and webinars

Join Siemens for face-to-face events around the globe. Siemens is committed to delivering next-gen electronic design solutions that meet the evolving needs of engineering teams.

Stop by our booth and learn about Xpedition, Hyperlynx and Valor tools.

Join Siemens EDA to learn how we collaborate with TSMC and mutual customers to develop innovative EDA technology.

Questa Verification IQ (VIQ) is a next-generation collaborative and data-driven verification solution; providing advanced analytics, enhanced collaboration, and comprehensive traceability by leveraging machine learning.

This event delivered updates on new AI/ML/big data, Verification IP, and DFT automation and techniques that you can adopt today to increase design and verification productivity.

In this webinar you will learn how Avery's scalable and customizable HBM Verification IP helps companies like Rambus verify industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance.

In this free seminar we showed how to navigate the complexity of Design-for-Test (DFT) and the related verification challenges so you can sign-off the design with confidence.

This keynote examines how semiconductor design is changing to enable rapid development and deployment of custom, application-optimized, SoC designs – from concept to in-life operation, as we route to a sustainable compute future.

Delve into how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation.

Demonstrating system simulations of a Versal example design will be a focal point of this webinar, showcasing QuestaSim’s support for Versal Adaptive SoC designs based on the Vitis™ hardware emulation flow; including QEMU co-sim

The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training, and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification.

This talk will show how HLS can be used to quickly create and assess multiple RTL implementations for an AI accelerator from a single algorithmic description.

Increasing reset signaling complexity is creating new Reset Domain Crossing (RDC) verification challenges that break “Gen 1” solutions. In this webinar we show how Questa RDC uses ML to rapidly root cause violations and errors.

Root causing RTL & testbench bugs can be tedious process, but in this webinar we will highlight innovations in QuestaSim that enable full debug visibility with the Visualizer debugger now included with every QuestaSim license.

Gate-level simulations (GLS) are a crucial step in ASCI/FPGA verification, but it can be a bottleneck. This webinar will describe how to manage Xs in GLS with the Siemens Avery SimXACT solution alongside your preferred simulator.

Increasing reset signaling complexity is creating new Reset Domain Crossing (RDC) verification challenges that are straining “Gen 1” solutions. In this webinar we will show new, advanced RDC techniques, methodology, and automation

In this presentation, we will introduce apps that provide advanced automated functional checking, secure data path verification, trustworthiness assessment, and equivalence checking to attack complex IC integrity challenges

Join us to learn pivotal design considerations for PCIe 5.0 and 6.0 IPs, how to verify an Integrity and Data Encryption (IDE) implementation, reach closure faster with Compliance Test Suites, and what's next for the standard.

Deep dive into Siemens Avery UCIe Verification IP, discussing key features such as dynamic block-level and SoC level testbench creation, traffic generation, error injection, debug features, and performance monitoring.

osmosis offers a unique opportunity to connect and engage with R&D experts and fellow participants. If you possess a compelling narrative of achievement, we cordially extend an invitation for you to unveil it at Osmosis.

The last thing you want when adding custom RISC-V instructions is to unintentionally insert a deep corner case bug. In this joint webinar with Codasip, we will show sim and formal verification flows to prevent this.

Join us to demystify formal coverage via user case studies that illustrate the detection of deep bugs that other methods might overlook.

Verifying RISC-V cores with custom extensions is a painful challenge. In this webinar we will present an automated, customer-proven exhaustive formal verification flow from ISA specs, with results from open-source cores.

This event featured new technologies and techniques that you can adopt today to increase your design and verification productivity.

This event featured new technologies and techniques that you can adopt today to increase your design and verification productivity.

This event featured new technologies and techniques that you can adopt today to increase your design and verification productivity.

This event featured new technologies and techniques that you can adopt today to increase your design and verification productivity.

osmosis A&D is about sharing the success in using formal techniques to address demanding verification of DO-254 compliant and other high-consequence systems - along with delivering sneak-previews of our future product roadmaps

This webinar introduces a simple and robust quantization methodology based on value range analysis.

This webinar will show how the Questa OneSpin Connectivity XL formal-based app can quickly specify, then exhaustively verify, all types of connectivity issues inside the largest SoC and 3DIC designs.

This webinar will describe the Avery and Questa protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or A&D applications.

Find out more about the webinar "Architectural Improvements for Low-Power and Functional Safety of Dataflow CNN Accelerators Using HLS".

In this webinar, you will learn how to implement concurrent assertions using SystemVerilog Assertions (SVA), and gain a deeper understanding of how they can complement your existing verification methodologies.

Learn how C++ and SystemC/MatchLib HLS is more than just converting SystemC to RTL. We’ll cover language choice, architecture exploration, power estimation and optimization that all work to deliver competitive RTL fast & cheap.

Learn how to design low-power, IPs/SOCs by including low-power techniques in your design flows and tracking power throughout the RTL development cycle to realize energy efficient designs. 

Design flow including HW/SW co-design and HLS that allows developers to migrate compute intensive functions from SW running on an embedded processor to a HW based accelerator as a loosely coupled bus-based peripheral.

Learn how you can use High-Level Synthesis to go from Python to synthesizable RTL to deploy a custom AI accelerator faster and easier than you thought possible. 

Osmosis is about sharing success in using formal techniques to solve IC verification challenges and networking with our R&D experts and piers in the IC verification field.

PLDA and Siemens EDA join to introduce you to PCIe 6.0, including architecture differences from prior generations, performance improvements, and how PCIe 6.0 compares from both a designer and verification perspective.

Cornell intros HiSparse: accelerator on sparse-matrix dense-vector multiplication. Using both HLS implementation and simulation, their sparse accelerators deliver promising speedup with increased bandwidth and energy efficiency.

FNAL demos that a NN autoencoder model can be implemented in a radiation-tolerant ASIC to perform lossy data compression. This alleviates the data transmission problem while preserving the detector energy profile's critical info.

Access key presentations from Tessent, customers & partners at ITC 2022.

Along with its associated workshops & tutorials, ITC is the place to discover new DFT technologies, IC test, yield learning & in-life monitoring & analytics.