Accelerated confidence in simulation-based verification of RTL designs with ARM AMBA bus interfaces such as AXI, AHB, APB, CHI, ACE
Enable system-on-chip (SoC) and IP developers to perform comprehensive functional verification of their IP and SOCs. Avery Verification IP for AMBA incorporates the full range of AMBA bus protocols (AXI4 – Full, Lite, Stream, AXI3, AHB, APB, CHI) master, slave and interconnects functionalities and ensure compliance to the AMBA standards.
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Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.
Insight and updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.