Best of Tessent at ITC 2021

Access the ITC 2021 presentations from Tessent technologists, customers, and partners from this page. Along with its associated workshops and tutorials, ITC is the best place to discover new technologies for IC test, bring up, yield learning, and in-life monitoring and analytics.

Diamond Supporter Presentations

Siemens is proud to be a Diamond Supporter of the International Test Conference. In the Diamond Supporter Presentations, you can learn more about the Tessent Streaming Scan Network technology that was launched at last year’s ITC.

Our commitment to innovation

Joe Sawicki, Executive Vice President, and Janusz Rajski, Vice President of Engineering at Siemens EDA, describe the key industry trends that drive Tessent’s innovation.

Future-ready with Streaming Scan Network

Mark Kassab, Engineering Director for Tessent ATPG & Compression at Siemens EDA, describes how SSN is not just an ideal SoC DFT solution today, but also creates a foundation for future DFT needs.

Enhancing test on 3GHz designs with SSN

Srinu Alampally, Master Engineer at Broadcom, explains SSN implementation and silicon results on a high-speed multi-CPU design.

SSN implementation on a large multi-die SoC

Dave Dehnert, Principal Engineer at Intel, describes the SSN implementation experience on a large, multi-die design.

Technical Program

Tessent has a long history of presenting award winning papers at ITC. At ITC 2021, we presented innovations in ATPG compression, 3D IC DFT, silicon lifecycle management, and security.

Special Session

3DIC Test Challenges, Trends, and Solutions

Wu Yang, Technical & Foundry Programs Manager at Siemens EDA, presents an EDA perspective on 3D IC test, including IEEE 1838 and 3D stack test methodology.

On Reduction of Deterministic Test Pattern Sets

Janusz Rajski, Vice President of Engineering at Siemens EDA, presents work on the current state of pattern compaction technology.

Security And Provisioning Through Test And Safety

Lee Harrison, Automotive Test Solutions Manager Siemens EDA, explores the issues of security challenges in IC test.

Using SLM to Monitor Automotive Electronics

Lee Harrison, Automotive Test Solutions Manager Siemens EDA, discusses using the tools of Silicon Lifecycle Management (SLM) to monitor the aging effects on automotive electronics.

SLS: Latency reduction and performance optimization

Aileen Ryan, Senior Director of Strategy at Siemens EDA, discusses techniques for latency reduction and performance optimization as part of an overall Silicon Lifecycle Solutions portfolio.

Partner Presentations

The Tessent Theater is a tradition on the ITC Exhibit floor. At every ITC, our partners present their experiences with Tessent technologies, reference flows, and collaboration projects.

Automating physical mapping on Arm IP with Tessent

Frank Frederick, Principal Design Engineer at Arm, covers automating physical mapping on Arm IP with Tessent MBIST shared bus learning.

Plug & Play DFT Solutions to HPC/AI

Joe Reynick, Technology Enablement Engineer at Siemens EDA, presents on behalf of Dongkwan Han of Samsung Foundry, about plug-and-play DFT solutions for high-performance and artificial intelligence SoCs.

Accelerating scan test with SSN and 1149.10 on V93000

Michael Braun, Product Manager at Advantest covers how to accelerate scan test with the Tessent Streaming Scan Network and IEEE 1149.10 on the V93000.

High-Speed Scan Testing with SSN & IEEE 1149.10

Ed Seng, Product Marketing Manager at Teradyne, presents high-speed scan testing with the Tessent Streaming Scan Network and IEEE 1149.10.

Accelerating pattern bring-up on high pin count designs

Arik Krantz, DFT Engineer at Broadcom, discusses accelerating pattern bring-up on high pin count designs.

Tessent Hierarchical DFT

Saket Goyal, Master Engineer at Broadcom, describes how his team used Tessent Hierarchical DFT to meet time-to-market challenges for their multi-billion transistor designs.

Tessent Presentations

Learn from Tessent experts about recent advances in the Tessent products, and how you can best leverage these in your DFT implementation.

Tessent Visualizer - New IJTAG Visualization and Debug

Marcin Lipinksi, Technical Product Owner at Siemens EDA, presents new features in Tessent for IJTAG visualization and debug.

ATPG Boost: Boost your test quality in less time

Bill Keller, Product Engineer at Siemens EDA, introduces ATPG Boost, a set of new capabilities in Tessent TestKompress that reduces test time, improves coverage, and increases throughput.

SSN and deterministic on-chip compare

Joe Reynick, Technology Enablement Engineer at Siemens EDA, describes deterministic on-chip compare with the Streaming Scan Network.

The SSN flexible architecture

Peter Orlando, Product Engineer at Siemens EDA, explains what makes the Tessent Streaming Scan Network architecture so flexible.

SSN packet basics

Joe Reynick, Technology Enablement Engineer at Siemens EDA, covers the basics of Streaming Scan Network data packets.

The power of SSN

Joe Reynick, Technology Enablement Engineer at Siemens EDA, explains why Tessent's packetized test solution, Streaming Scan Network, is a powerful tool for improving IC test.

Tessent MemoryBIST shared bus learning

This presentation from Harshitha Kodali, Product Engineer at Siemens EDA, gives a technical overview of the Tessent MemoryBIST shared bus learning.

Timing-aware ATPG small delay defect detection

Ron Press, Director of Technology Enablement at Siemens EDA, describes how to catch small delay defects.

Reversible chain technology improves chain diagnosis

Matt Knowles, Director of Operations Product Management at Siemens EDA, describes a novel reversible scan chain technology that improves chain diagnosis resolution by 4X.

Critical area weighted pattern optimization

Ron Press, Technology Enablement Director at Siemens EDA, explains how to use critical-area based pattern optimization to get the most out of defect-oriented test and advanced fault models.