High-Level Synthesis & Verification

Worried your next RTL project will be late? Will your new “secret sauce” design suffice or will it consume too much power? How will you verify it’s functionally correct and optimally crafted before committing to RTL? Catapult High-Level Synthesis (HLS) & High-Level Verification changes the game.

HLS & HLV Upcoming Events HLS & HLV Resource Library

TRENDS & TECHNOLOGIES

RTL Design & Verification is Too Slow & Expensive

RTL productivity, especially for new and complex value-add blocks, has stalled. The design and verification challenges of creating new and novel architectures that deliver advantages in silicon for Wireless, 5G, ML, or Video/Image processing isn’t making life any easier for design teams.

Architecture Exploration

Will your hardware be system performance limited? Did you pick the right fundamental memory architecture? Or did you only find out during system integration and test that real-world performance isn’t what you needed?

Catapult your design

Are You Still Debugging RTL?

Discovering bugs late in RTL means missed opportunities, less competitive silicon, tape out delays and ECO headaches. HLS design and verification delivers right-first-time RTL designs, with reduced server and tool cost.

Find bugs faster with HLS

Optimal Power Performance and Area

Delivering an optimal balance of Performance, Power and Area for your design needs is hard. Too little performance, too much power or too much area and you might miss a product cycle. Leverage HLS to design better and faster.

Optimize your PPA

Catapult High-Level Synthesis Solutions

Catapult Synthesis solutions from Siemens deliver C++ and SystemC language support, FPGA and ASIC independence, ASIC power estimation and optimization plus the latest in Physically aware multi-VT area and performance optimization.

C++/SystemC Synthesis

A comprehensive HLS tool that covers all your needs for the most complex ASIC and FPGA designs.

Low-Power Solutions

When it comes to early architecture power estimation, plus optimizing for low-power ASIC RTL, Catapult has what you need.

Physically Aware HLS

As geometries shrink, Catapult keeps pace with design portability, physical downstream data, and exceptional QoR.

Catapult High-Level Verification Solutions

Everything you need to accelerate your High-Level Verification flow. Reduce Verification time and costs by up to 80% leveraging Design Checking, Code and Functional Coverage plus Formal.

Catapult Design Checker

Lint and formal analysis to validate your HLS designs for correctness before synthesis. Avoid design problems and QoR issues that can occur when coding for HLS.

Catapult Coverage

Provides HLS-aware code coverage, including statement, branch, FEC, toggle and array access coverage. SV-inspired functional coverage with support for covergroups, coverpoints, bins and crosses.

Catapult Formal Verification Tools

Formally find mistakes, ambiguities and undesirable design issues, user constraints problems early in the HLS process. Even with differences in timing, and interfaces Catapult Formal enables verification and coverage closure flow.

SLEC System

Check the correctness of RTL against your High-Level models using SLEC. Enabling proof that specification and implementation are identical despite differences in language, timing, or abstraction.