Catapult High-Level Synthesis and Verification

The broadest portfolio of hardware design solutions for C++ and SystemC-based
High-Level Synthesis (HLS). Catapult's physically-aware, multi-VT mode, with
Low-Power estimation and optimization, plus a range of leading Verification
solutions make HLS from Siemens more than just "C to RTL".

Catapult High-Level Synthesis Solutions

Catapult Synthesis solutions from Siemens deliver C++ and SystemC language support, FPGA and ASIC independence, ASIC power estimation and optimization plus the latest in Physically aware multi-VT area and performance optimization.

C++/SystemC Synthesis

A comprehensive HLS solution covering all your needs for the most complex ASIC and FPGA designs.

View Product

Low-Power Solutions

When it comes to early architecture power estimation, plus optimizing for low-power ASIC RTL, Catapult has what you need.

View Product

Physically Aware HLS

As geometries shrink, Catapult keeps pace with design portability, physical downstream data, and exceptional Quality of Results.

View Product

Catapult High-Level Verification Solutions

Everything you need to accelerate your High-Level Verification flow. Reduce Verification time and costs by up to 80% leveraging Design Checking, Code and Functional Coverage plus Formal.

Catapult Design Checker

Lint and formal analysis to validate your HLS designs for correctness before synthesis. Avoid design problems and QoR issues that can occur when coding for HLS.

View Product

Catapult Coverage

Provides HLS-aware code coverage, including statement, branch, FEC, toggle and array access coverage. SV-inspired functional coverage with support for covergroups, coverpoints, bins and crosses.

View Product

Catapult Formal Verification Tools

Formally find mistakes, ambiguities and undesirable design issues, user constraints problems early in the HLS process. Even with differences in timing, and interfaces Catapult Formal enables verification and coverage closure flow.

View Product

SLEC System

Check the correctness of RTL against your High-Level models using SLEC. Enabling proof that specification and implementation are identical despite differences in language, timing, or abstraction.

View Product