Catapult High-Level Synthesis and Verification

A comprehensive HLS solution covering all your needs for the most complex ASIC and FPGA designs.

When it comes to early architecture power estimation, plus optimizing for low-power ASIC RTL, Catapult has what you need.

As geometries shrink, Catapult keeps pace with design portability, physical downstream data, and exceptional Quality of Results.

Lint and formal analysis to validate your HLS designs for correctness before synthesis. Avoid design problems and QoR issues that can occur when coding for HLS.

Provides HLS-aware code coverage, including statement, branch, FEC, toggle and array access coverage. SV-inspired functional coverage with support for covergroups, coverpoints, bins and crosses.

Formally find mistakes, ambiguities and undesirable design issues, user constraints problems early in the HLS process. Even with differences in timing, and interfaces Catapult Formal enables verification and coverage closure flow.

Check the correctness of RTL against your High-Level models using SLEC. Enabling proof that specification and implementation are identical despite differences in language, timing, or abstraction.